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johnwalker

johnwalker (hace 1256 dias) (0)

 

I am looking for iformation on the masking of data write in embedded SRAM for both FPGA and ASIC in today's 28nm processes. What is the approximate cost of byte or bit mask over normal 32-bit SRAM in ASIC? 
With regard to FPGA, would the usage of dual port RAM be still the same utilization as singl port RAM, Since FPGA block RAM is dual port by default? Will adding a mask affect the resource utilization?  
My design is to minimize unnecessary memory accesses, i.e. reduce read change write operations if possible. 
For more details Small Business Video

I am looking for iformation on the masking of data write in embedded SRAM for both FPGA and ASIC in today's 28nm processes. What is the approximate cost of byte or bit mask over normal 32-bit SRAM in ASIC? 

With regard to FPGA, would the usage of dual port RAM be still the same utilization as singl port RAM, Since FPGA block RAM is dual port by default? Will adding a mask affect the resource utilization?  

My design is to minimize unnecessary memory accesses, i.e. reduce read change write operations if possible. 

 

For more details Small Business Video